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Correct tsd layout graph

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Augmented the tsd layout graph so that the two recently added fields,
`offset_state` and `bytes_until_sample`, are properly reflected.
As is shown, the cache footprint is 16 bytes larger than before.
This commit is contained in:
Yinan Zhang 2019-06-06 09:22:10 -07:00 committed by Qi Wang
parent ea6b3e973b
commit 56c8ecffc1
1 changed files with 6 additions and 2 deletions
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8
include/jemalloc/internal/tsd.h
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@ -20,6 +20,7 @@
* e: tcache_enabled * e: tcache_enabled
* m: thread_allocated (config_stats) * m: thread_allocated (config_stats)
* f: thread_deallocated (config_stats) * f: thread_deallocated (config_stats)
* b: bytes_until_sample (config_prof)
* p: prof_tdata (config_prof) * p: prof_tdata (config_prof)
* c: rtree_ctx (rtree cache accessed on deallocation) * c: rtree_ctx (rtree cache accessed on deallocation)
* t: tcache * t: tcache
@ -27,6 +28,7 @@
* d: arenas_tdata_bypass * d: arenas_tdata_bypass
* r: reentrancy_level * r: reentrancy_level
* x: narenas_tdata * x: narenas_tdata
* v: offset_state
* i: iarena * i: iarena
* a: arena * a: arena
* o: arenas_tdata * o: arenas_tdata
@ -35,11 +37,13 @@
* Use a compact layout to reduce cache footprint. * Use a compact layout to reduce cache footprint.
* +--- 64-bit and 64B cacheline; 1B each letter; First byte on the left. ---+ * +--- 64-bit and 64B cacheline; 1B each letter; First byte on the left. ---+
* |---------------------------- 1st cacheline ----------------------------| * |---------------------------- 1st cacheline ----------------------------|
* | sedrxxxx mmmmmmmm ffffffff pppppppp [c * 32 ........ ........ .......] | * | sedrxxxx vvvvvvvv mmmmmmmm ffffffff bbbbbbbb pppppppp [c * 16 .......] |
* |---------------------------- 2nd cacheline ----------------------------| * |---------------------------- 2nd cacheline ----------------------------|
* | [c * 64 ........ ........ ........ ........ ........ ........ .......] | * | [c * 64 ........ ........ ........ ........ ........ ........ .......] |
* |---------------------------- 3nd cacheline ----------------------------| * |---------------------------- 3nd cacheline ----------------------------|
* | [c * 32 ........ ........ .......] iiiiiiii aaaaaaaa oooooooo [t...... | * | [c * 48 ........ ........ ........ ........ .......] iiiiiiii aaaaaaaa |
* +---------------------------- 4th cacheline ----------------------------+
* | oooooooo [t...... ........ ........ ........ ........ ........ ........ |
* +-------------------------------------------------------------------------+ * +-------------------------------------------------------------------------+
* Note: the entire tcache is embedded into TSD and spans multiple cachelines. * Note: the entire tcache is embedded into TSD and spans multiple cachelines.
* *