Correct tsd layout graph
Augmented the tsd layout graph so that the two recently added fields, `offset_state` and `bytes_until_sample`, are properly reflected. As is shown, the cache footprint is 16 bytes larger than before.
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@ -20,6 +20,7 @@
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* e: tcache_enabled
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* m: thread_allocated (config_stats)
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* f: thread_deallocated (config_stats)
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* b: bytes_until_sample (config_prof)
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* p: prof_tdata (config_prof)
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* c: rtree_ctx (rtree cache accessed on deallocation)
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* t: tcache
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@ -27,6 +28,7 @@
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* d: arenas_tdata_bypass
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* r: reentrancy_level
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* x: narenas_tdata
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* v: offset_state
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* i: iarena
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* a: arena
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* o: arenas_tdata
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@ -35,11 +37,13 @@
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* Use a compact layout to reduce cache footprint.
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* +--- 64-bit and 64B cacheline; 1B each letter; First byte on the left. ---+
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* |---------------------------- 1st cacheline ----------------------------|
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* | sedrxxxx mmmmmmmm ffffffff pppppppp [c * 32 ........ ........ .......] |
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* | sedrxxxx vvvvvvvv mmmmmmmm ffffffff bbbbbbbb pppppppp [c * 16 .......] |
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* |---------------------------- 2nd cacheline ----------------------------|
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* | [c * 64 ........ ........ ........ ........ ........ ........ .......] |
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* |---------------------------- 3nd cacheline ----------------------------|
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* | [c * 32 ........ ........ .......] iiiiiiii aaaaaaaa oooooooo [t...... |
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* | [c * 48 ........ ........ ........ ........ .......] iiiiiiii aaaaaaaa |
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* +---------------------------- 4th cacheline ----------------------------+
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* | oooooooo [t...... ........ ........ ........ ........ ........ ........ |
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* +-------------------------------------------------------------------------+
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* Note: the entire tcache is embedded into TSD and spans multiple cachelines.
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*
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