Stats, CTL: Expose new tcache settings.
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parent
ee72bf1cfd
commit
7503b5b33a
28
src/ctl.c
28
src/ctl.c
@ -103,9 +103,15 @@ CTL_PROTO(opt_zero)
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CTL_PROTO(opt_utrace)
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CTL_PROTO(opt_xmalloc)
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CTL_PROTO(opt_tcache)
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CTL_PROTO(opt_lg_tcache_max)
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CTL_PROTO(opt_tcache_nslots_small_min)
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CTL_PROTO(opt_tcache_nslots_small_max)
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CTL_PROTO(opt_tcache_nslots_large)
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CTL_PROTO(opt_lg_tcache_nslots_mul)
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CTL_PROTO(opt_tcache_gc_incr_bytes)
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CTL_PROTO(opt_tcache_gc_delay_bytes)
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CTL_PROTO(opt_thp)
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CTL_PROTO(opt_lg_extent_max_active_fit)
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CTL_PROTO(opt_lg_tcache_max)
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CTL_PROTO(opt_prof)
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CTL_PROTO(opt_prof_prefix)
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CTL_PROTO(opt_prof_active)
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@ -340,9 +346,17 @@ static const ctl_named_node_t opt_node[] = {
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{NAME("utrace"), CTL(opt_utrace)},
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{NAME("xmalloc"), CTL(opt_xmalloc)},
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{NAME("tcache"), CTL(opt_tcache)},
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{NAME("lg_tcache_max"), CTL(opt_lg_tcache_max)},
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{NAME("tcache_nslots_small_min"),
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CTL(opt_tcache_nslots_small_min)},
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{NAME("tcache_nslots_small_max"),
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CTL(opt_tcache_nslots_small_max)},
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{NAME("tcache_nslots_large"), CTL(opt_tcache_nslots_large)},
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{NAME("lg_tcache_nslots_mul"), CTL(opt_lg_tcache_nslots_mul)},
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{NAME("tcache_gc_incr_bytes"), CTL(opt_tcache_gc_incr_bytes)},
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{NAME("tcache_gc_delay_bytes"), CTL(opt_tcache_gc_delay_bytes)},
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{NAME("thp"), CTL(opt_thp)},
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{NAME("lg_extent_max_active_fit"), CTL(opt_lg_extent_max_active_fit)},
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{NAME("lg_tcache_max"), CTL(opt_lg_tcache_max)},
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{NAME("prof"), CTL(opt_prof)},
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{NAME("prof_prefix"), CTL(opt_prof_prefix)},
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{NAME("prof_active"), CTL(opt_prof_active)},
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@ -1793,10 +1807,18 @@ CTL_RO_NL_CGEN(config_fill, opt_zero, opt_zero, bool)
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CTL_RO_NL_CGEN(config_utrace, opt_utrace, opt_utrace, bool)
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CTL_RO_NL_CGEN(config_xmalloc, opt_xmalloc, opt_xmalloc, bool)
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CTL_RO_NL_GEN(opt_tcache, opt_tcache, bool)
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CTL_RO_NL_GEN(opt_lg_tcache_max, opt_lg_tcache_max, ssize_t)
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CTL_RO_NL_GEN(opt_tcache_nslots_small_min, opt_tcache_nslots_small_min,
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unsigned)
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CTL_RO_NL_GEN(opt_tcache_nslots_small_max, opt_tcache_nslots_small_max,
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unsigned)
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CTL_RO_NL_GEN(opt_tcache_nslots_large, opt_tcache_nslots_large, unsigned)
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CTL_RO_NL_GEN(opt_lg_tcache_nslots_mul, opt_lg_tcache_nslots_mul, ssize_t)
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CTL_RO_NL_GEN(opt_tcache_gc_incr_bytes, opt_tcache_gc_incr_bytes, size_t)
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CTL_RO_NL_GEN(opt_tcache_gc_delay_bytes, opt_tcache_gc_delay_bytes, size_t)
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CTL_RO_NL_GEN(opt_thp, thp_mode_names[opt_thp], const char *)
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CTL_RO_NL_GEN(opt_lg_extent_max_active_fit, opt_lg_extent_max_active_fit,
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size_t)
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CTL_RO_NL_GEN(opt_lg_tcache_max, opt_lg_tcache_max, ssize_t)
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CTL_RO_NL_CGEN(config_prof, opt_prof, opt_prof, bool)
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CTL_RO_NL_CGEN(config_prof, opt_prof_prefix, opt_prof_prefix, const char *)
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CTL_RO_NL_CGEN(config_prof, opt_prof_active, opt_prof_active, bool)
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@ -1107,6 +1107,12 @@ stats_general_print(emitter_t *emitter) {
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OPT_WRITE_BOOL("xmalloc")
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OPT_WRITE_BOOL("tcache")
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OPT_WRITE_SSIZE_T("lg_tcache_max")
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OPT_WRITE_UNSIGNED("tcache_nslots_small_min")
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OPT_WRITE_UNSIGNED("tcache_nslots_small_max")
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OPT_WRITE_UNSIGNED("tcache_nslots_large")
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OPT_WRITE_SSIZE_T("lg_tcache_nslots_mul")
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OPT_WRITE_SIZE_T("tcache_gc_incr_bytes")
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OPT_WRITE_SIZE_T("tcache_gc_delay_bytes")
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OPT_WRITE_CHAR_P("thp")
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OPT_WRITE_BOOL("prof")
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OPT_WRITE_CHAR_P("prof_prefix")
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12
src/tcache.c
12
src/tcache.c
@ -33,6 +33,12 @@ unsigned opt_tcache_nslots_large = 20;
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*/
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ssize_t opt_lg_tcache_nslots_mul = -1;
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/*
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* Number of allocation bytes between tcache incremental GCs. Again, this
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* default just seems to work well; more tuning is possible.
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*/
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size_t opt_tcache_gc_incr_bytes = 65536;
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/*
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* With default settings, we may end up flushing small bins frequently with
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* small flush amounts. To limit this tendency, we can set a number of bytes to
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@ -47,12 +53,6 @@ ssize_t opt_lg_tcache_nslots_mul = -1;
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*/
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size_t opt_tcache_gc_delay_bytes = 0;
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/*
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* Number of allocation bytes between tcache incremental GCs. Again, this
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* default just seems to work well; more tuning is possible.
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*/
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size_t opt_tcache_gc_incr_bytes = 65536;
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cache_bin_info_t *tcache_bin_info;
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/* Total stack size required (per tcache). Include the padding above. */
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