From 89fe8ee6bf7a23556350d883a310c0224a171879 Mon Sep 17 00:00:00 2001
From: Jonathan Swinney <jswinney@amazon.com>
Date: Thu, 6 Jan 2022 17:09:34 +0000
Subject: [PATCH] Use the isb instruction instead of yield for spin locks on
 arm

isb introduces a small delay which is closer to the x86 pause instruction.
---
 configure.ac | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/configure.ac b/configure.ac
index 49a12ac8..3303badf 100644
--- a/configure.ac
+++ b/configure.ac
@@ -425,14 +425,15 @@ case "${host_cpu}" in
 	;;
   aarch64|arm*)
 	HAVE_CPU_SPINWAIT=1
-    AC_CACHE_VAL([je_cv_yield],
-      [JE_COMPILABLE([yield instruction], [],
-                    [[__asm__ volatile("yield"); return 0;]],
-                    [je_cv_yield])])
-	if test "x${je_cv_yield}" = "xyes" ; then
-	CPU_SPINWAIT='__asm__ volatile("yield")'
+	dnl isb is a better equivalent to the pause instruction on x86.
+	AC_CACHE_VAL([je_cv_isb],
+	  [JE_COMPILABLE([isb instruction], [],
+			[[__asm__ volatile("isb"); return 0;]],
+			[je_cv_isb])])
+	if test "x${je_cv_isb}" = "xyes" ; then
+	    CPU_SPINWAIT='__asm__ volatile("isb")'
 	fi
-    ;;
+	;;
   *)
 	HAVE_CPU_SPINWAIT=0
 	;;