Update the tsd description.
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@ -17,21 +17,27 @@
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* Thread-Specific-Data layout
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* --- data accessed on tcache fast path: state, rtree_ctx, stats ---
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* s: state
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* e: tcache_enabled
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* m: thread_allocated
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* k: thread_allocated_next_event_fast
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* f: thread_deallocated
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* h: thread_deallocated_next_event_fast
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* c: rtree_ctx (rtree cache accessed on deallocation)
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* t: tcache
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* --- data not accessed on tcache fast path: arena-related fields ---
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* e: tcache_enabled
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* d: arenas_tdata_bypass
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* r: reentrancy_level
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* x: narenas_tdata
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* n: narenas_tdata
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* l: thread_allocated_last_event
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* j: thread_allocated_next_event
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* q: thread_deallocated_last_event
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* u: thread_deallocated_next_event
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* g: tcache_gc_event_wait
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* y: tcache_gc_dalloc_event_wait
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* w: prof_sample_event_wait (config_prof)
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* x: prof_sample_last_event (config_prof)
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* z: stats_interval_event_wait
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* e: stats_interval_last_event
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* p: prof_tdata (config_prof)
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* v: prng_state
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* i: iarena
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@ -43,15 +49,15 @@
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* Use a compact layout to reduce cache footprint.
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* +--- 64-bit and 64B cacheline; 1B each letter; First byte on the left. ---+
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* |---------------------------- 1st cacheline ----------------------------|
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* | sedrxxxx mmmmmmmm kkkkkkkk ffffffff [c * 32 ........ ........ .......] |
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* | sedrnnnn mmmmmmmm kkkkkkkk ffffffff hhhhhhhh [c * 24 ........ ........]|
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* |---------------------------- 2nd cacheline ----------------------------|
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* | [c * 64 ........ ........ ........ ........ ........ ........ .......] |
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* | [c * 64 ........ ........ ........ ........ ........ ........ ........]|
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* |---------------------------- 3nd cacheline ----------------------------|
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* | [c * 32 ........ ........ .......] llllllll jjjjjjjj gggggggg wwwwwwww |
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* | [c * 40 ........ ........ ........ .......] llllllll jjjjjjjj qqqqqqqq |
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* +---------------------------- 4th cacheline ----------------------------+
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* | xxxxxxxx pppppppp vvvvvvvv iiiiiiii aaaaaaaa oooooooo [b...... ........ |
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* +---------------------------- 5th cacheline ----------------------------+
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* | ........ ........ ..b][t.. ........ ........ ........ ........ ........ |
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* | uuuuuuuu gggggggg yyyyyyyy wwwwwwww xxxxxxxx zzzzzzzz eeeeeeee pppppppp |
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* +---------------------------- 5th and after ----------------------------+
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* | vvvvvvvv iiiiiiii aaaaaaaa oooooooo [b * 40; then embedded tcache ..... |
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* +-------------------------------------------------------------------------+
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* Note: the entire tcache is embedded into TSD and spans multiple cachelines.
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*
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