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Update the tsd description.

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Qi Wang 2020-02-03 23:59:31 -08:00 committed by Qi Wang
parent e896522616
commit c6bfe55857
1 changed files with 14 additions and 8 deletions
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22
include/jemalloc/internal/tsd.h
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@ -17,21 +17,27 @@
* Thread-Specific-Data layout * Thread-Specific-Data layout
* --- data accessed on tcache fast path: state, rtree_ctx, stats --- * --- data accessed on tcache fast path: state, rtree_ctx, stats ---
* s: state * s: state
* e: tcache_enabled
* m: thread_allocated * m: thread_allocated
* k: thread_allocated_next_event_fast * k: thread_allocated_next_event_fast
* f: thread_deallocated * f: thread_deallocated
* h: thread_deallocated_next_event_fast
* c: rtree_ctx (rtree cache accessed on deallocation) * c: rtree_ctx (rtree cache accessed on deallocation)
* t: tcache * t: tcache
* --- data not accessed on tcache fast path: arena-related fields --- * --- data not accessed on tcache fast path: arena-related fields ---
* e: tcache_enabled
* d: arenas_tdata_bypass * d: arenas_tdata_bypass
* r: reentrancy_level * r: reentrancy_level
* x: narenas_tdata * n: narenas_tdata
* l: thread_allocated_last_event * l: thread_allocated_last_event
* j: thread_allocated_next_event * j: thread_allocated_next_event
* q: thread_deallocated_last_event
* u: thread_deallocated_next_event
* g: tcache_gc_event_wait * g: tcache_gc_event_wait
* y: tcache_gc_dalloc_event_wait
* w: prof_sample_event_wait (config_prof) * w: prof_sample_event_wait (config_prof)
* x: prof_sample_last_event (config_prof) * x: prof_sample_last_event (config_prof)
* z: stats_interval_event_wait
* e: stats_interval_last_event
* p: prof_tdata (config_prof) * p: prof_tdata (config_prof)
* v: prng_state * v: prng_state
* i: iarena * i: iarena
@ -43,15 +49,15 @@
* Use a compact layout to reduce cache footprint. * Use a compact layout to reduce cache footprint.
* +--- 64-bit and 64B cacheline; 1B each letter; First byte on the left. ---+ * +--- 64-bit and 64B cacheline; 1B each letter; First byte on the left. ---+
* |---------------------------- 1st cacheline ----------------------------| * |---------------------------- 1st cacheline ----------------------------|
* | sedrxxxx mmmmmmmm kkkkkkkk ffffffff [c * 32 ........ ........ .......] | * | sedrnnnn mmmmmmmm kkkkkkkk ffffffff hhhhhhhh [c * 24 ........ ........]|
* |---------------------------- 2nd cacheline ----------------------------| * |---------------------------- 2nd cacheline ----------------------------|
* | [c * 64 ........ ........ ........ ........ ........ ........ .......] | * | [c * 64 ........ ........ ........ ........ ........ ........ ........]|
* |---------------------------- 3nd cacheline ----------------------------| * |---------------------------- 3nd cacheline ----------------------------|
* | [c * 32 ........ ........ .......] llllllll jjjjjjjj gggggggg wwwwwwww | * | [c * 40 ........ ........ ........ .......] llllllll jjjjjjjj qqqqqqqq |
* +---------------------------- 4th cacheline ----------------------------+ * +---------------------------- 4th cacheline ----------------------------+
* | xxxxxxxx pppppppp vvvvvvvv iiiiiiii aaaaaaaa oooooooo [b...... ........ | * | uuuuuuuu gggggggg yyyyyyyy wwwwwwww xxxxxxxx zzzzzzzz eeeeeeee pppppppp |
* +---------------------------- 5th cacheline ----------------------------+ * +---------------------------- 5th and after ----------------------------+
* | ........ ........ ..b][t.. ........ ........ ........ ........ ........ | * | vvvvvvvv iiiiiiii aaaaaaaa oooooooo [b * 40; then embedded tcache ..... |
* +-------------------------------------------------------------------------+ * +-------------------------------------------------------------------------+
* Note: the entire tcache is embedded into TSD and spans multiple cachelines. * Note: the entire tcache is embedded into TSD and spans multiple cachelines.
* *