Introduce a backport of C11 atomics
This introduces a backport of C11 atomics. It has four implementations; ranked in order of preference, they are: - GCC/Clang __atomic builtins - GCC/Clang __sync builtins - MSVC _Interlocked builtins - C11 atomics, from <stdatomic.h> The primary advantages are: - Close adherence to the standard API gives us a defined memory model. - Type safety: atomic objects are now separate types from non-atomic ones, so that it's impossible to mix up atomic and non-atomic updates (which is undefined behavior that compilers are starting to take advantage of). - Efficiency: we can specify ordering for operations, avoiding fences and atomic operations on strongly ordered architectures (example: `atomic_write_u32(ptr, val);` involves a CAS loop, whereas `atomic_store(ptr, val, ATOMIC_RELEASE);` is a plain store. This diff leaves in the current atomics API (implementing them in terms of the backport). This lets us transition uses over piecemeal. Testing: This is by nature hard to test. I've manually tested the first three options on Linux on gcc by futzing with the #defines manually, on freebsd with gcc and clang, on MSVC, and on OS X with clang. All of these were x86 machines though, and we don't have any test infrastructure set up for non-x86 platforms.
This commit is contained in:
David Goldblatt
committed by
David Goldblatt
David Goldblatt
parent
957b8c5f21
commit
d4ac7582f3
191
include/jemalloc/internal/atomic_gcc_sync.h
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191
include/jemalloc/internal/atomic_gcc_sync.h
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#ifndef JEMALLOC_INTERNAL_ATOMIC_GCC_SYNC_H
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#define JEMALLOC_INTERNAL_ATOMIC_GCC_SYNC_H
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#define ATOMIC_INIT(...) {__VA_ARGS__}
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typedef enum {
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atomic_memory_order_relaxed,
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atomic_memory_order_acquire,
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atomic_memory_order_release,
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atomic_memory_order_acq_rel,
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atomic_memory_order_seq_cst
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} atomic_memory_order_t;
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ATOMIC_INLINE void
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atomic_fence(atomic_memory_order_t mo) {
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/* Easy cases first: no barrier, and full barrier. */
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if (mo == atomic_memory_order_relaxed) {
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asm volatile("" ::: "memory");
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return;
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}
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if (mo == atomic_memory_order_seq_cst) {
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asm volatile("" ::: "memory");
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__sync_synchronize();
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asm volatile("" ::: "memory");
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return;
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}
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asm volatile("" ::: "memory");
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# if defined(__i386__) || defined(__x86_64__)
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/* This is implicit on x86. */
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# elif defined(__ppc__)
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asm volatile("lwsync");
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# elif defined(__sparc__) && defined(__arch64__)
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if (mo == atomic_memory_order_acquire) {
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asm volatile("membar #LoadLoad | #LoadStore");
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} else if (mo == atomic_memory_order_release) {
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asm volatile("membar #LoadStore | #StoreStore");
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} else {
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asm volatile("membar #LoadLoad | #LoadStore | #StoreStore");
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}
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# else
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__sync_synchronize();
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# endif
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asm volatile("" ::: "memory");
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}
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/*
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* A correct implementation of seq_cst loads and stores on weakly ordered
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* architectures could do either of the following:
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* 1. store() is weak-fence -> store -> strong fence, load() is load ->
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* strong-fence.
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* 2. store() is strong-fence -> store, load() is strong-fence -> load ->
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* weak-fence.
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* The tricky thing is, load() and store() above can be the load or store
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* portions of a gcc __sync builtin, so we have to follow GCC's lead, which
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* means going with strategy 2.
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* On strongly ordered architectures, the natural strategy is to stick a strong
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* fence after seq_cst stores, and have naked loads. So we want the strong
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* fences in different places on different architectures.
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* atomic_pre_sc_load_fence and atomic_post_sc_store_fence allow us to
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* accomplish this.
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*/
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ATOMIC_INLINE void
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atomic_pre_sc_load_fence() {
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# if defined(__i386__) || defined(__x86_64__) || \
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(defined(__sparc__) && defined(__arch64__))
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atomic_fence(atomic_memory_order_relaxed);
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# else
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atomic_fence(atomic_memory_order_seq_cst);
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# endif
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}
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ATOMIC_INLINE void
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atomic_post_sc_store_fence() {
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# if defined(__i386__) || defined(__x86_64__) || \
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(defined(__sparc__) && defined(__arch64__))
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atomic_fence(atomic_memory_order_seq_cst);
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# else
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atomic_fence(atomic_memory_order_relaxed);
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# endif
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}
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#define JEMALLOC_GENERATE_ATOMICS(type, short_type, \
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/* unused */ lg_size) \
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typedef struct { \
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type volatile repr; \
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} atomic_##short_type##_t; \
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\
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ATOMIC_INLINE type \
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atomic_load_##short_type(const atomic_##short_type##_t *a, \
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atomic_memory_order_t mo) { \
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if (mo == atomic_memory_order_seq_cst) { \
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atomic_pre_sc_load_fence(); \
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} \
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type result = a->repr; \
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if (mo != atomic_memory_order_relaxed) { \
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atomic_fence(atomic_memory_order_acquire); \
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} \
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return result; \
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} \
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\
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ATOMIC_INLINE void \
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atomic_store_##short_type(atomic_##short_type##_t *a, \
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type val, atomic_memory_order_t mo) { \
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if (mo != atomic_memory_order_relaxed) { \
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atomic_fence(atomic_memory_order_release); \
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} \
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a->repr = val; \
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if (mo == atomic_memory_order_seq_cst) { \
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atomic_post_sc_store_fence(); \
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} \
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} \
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\
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ATOMIC_INLINE type \
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atomic_exchange_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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/* \
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* Because of FreeBSD, we care about gcc 4.2, which doesn't have\
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* an atomic exchange builtin. We fake it with a CAS loop. \
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*/ \
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while (true) { \
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type old = a->repr; \
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if (__sync_bool_compare_and_swap(&a->repr, old, val)) { \
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return old; \
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} \
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} \
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} \
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\
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ATOMIC_INLINE bool \
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atomic_compare_exchange_weak_##short_type(atomic_##short_type##_t *a, \
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type *expected, type desired, atomic_memory_order_t success_mo, \
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atomic_memory_order_t failure_mo) { \
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type prev = __sync_val_compare_and_swap(&a->repr, *expected, \
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desired); \
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if (prev == *expected) { \
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return true; \
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} else { \
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*expected = prev; \
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return false; \
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} \
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} \
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ATOMIC_INLINE bool \
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atomic_compare_exchange_strong_##short_type(atomic_##short_type##_t *a, \
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type *expected, type desired, atomic_memory_order_t success_mo, \
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atomic_memory_order_t failure_mo) { \
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type prev = __sync_val_compare_and_swap(&a->repr, *expected, \
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desired); \
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if (prev == *expected) { \
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return true; \
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} else { \
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*expected = prev; \
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return false; \
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} \
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}
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#define JEMALLOC_GENERATE_INT_ATOMICS(type, short_type, \
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/* unused */ lg_size) \
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JEMALLOC_GENERATE_ATOMICS(type, short_type, /* unused */ lg_size) \
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\
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ATOMIC_INLINE type \
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atomic_fetch_add_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_add(&a->repr, val); \
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} \
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\
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ATOMIC_INLINE type \
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atomic_fetch_sub_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_sub(&a->repr, val); \
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} \
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\
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ATOMIC_INLINE type \
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atomic_fetch_and_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_and(&a->repr, val); \
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} \
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\
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ATOMIC_INLINE type \
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atomic_fetch_or_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_or(&a->repr, val); \
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} \
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\
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ATOMIC_INLINE type \
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atomic_fetch_xor_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_xor(&a->repr, val); \
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}
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#endif /* JEMALLOC_INTERNAL_ATOMIC_GCC_SYNC_H */
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