Qi Wang 3c9c41edb2 Improve rtree cache with a two-level cache design. ... Two levels of rcache is implemented: a direct mapped cache as L1, combined with a LRU cache as L2. The L1 cache offers low cost on cache hit, but could suffer collision under circumstances. This is complemented by the L2 LRU cache, which is slower on cache access (overhead from linear search + reordering), but solves collison of L1 rather well.		2017-04-17 12:05:23 -07:00
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jemalloc	Improve rtree cache with a two-level cache design.	2017-04-17 12:05:23 -07:00
msvc_compat	Replace tabs following #define with spaces.	2017-01-20 21:45:53 -08:00