41e0b857be
Header files are now self-contained, which makes the relationships between the files clearer, and crucially allows LSP tools like `clangd` to function correctly in all of our header files. I have verified that the headers are self-contained (aside from the various Windows shims) by compiling them as if they were C files – in a follow-up commit I plan to add this to CI to ensure we don't regress on this front.
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
#ifndef JEMALLOC_INTERNAL_INLINES_A_H
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#define JEMALLOC_INTERNAL_INLINES_A_H
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#include "jemalloc/internal/jemalloc_preamble.h"
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#include "jemalloc/internal/arena_externs.h"
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#include "jemalloc/internal/arena_types.h"
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#include "jemalloc/internal/atomic.h"
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#include "jemalloc/internal/bit_util.h"
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#include "jemalloc/internal/jemalloc_internal_types.h"
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#include "jemalloc/internal/sc.h"
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#include "jemalloc/internal/tcache_externs.h"
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#include "jemalloc/internal/ticker.h"
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JEMALLOC_ALWAYS_INLINE malloc_cpuid_t
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malloc_getcpu(void) {
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assert(have_percpu_arena);
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#if defined(_WIN32)
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return GetCurrentProcessorNumber();
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#elif defined(JEMALLOC_HAVE_SCHED_GETCPU)
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return (malloc_cpuid_t)sched_getcpu();
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#elif defined(JEMALLOC_HAVE_RDTSCP)
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unsigned int ax, cx, dx;
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asm volatile("rdtscp" : "=a"(ax), "=d"(dx), "=c"(cx) ::);
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return (malloc_cpuid_t)(dx & 0xfff);
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#elif defined(__aarch64__) && defined(__APPLE__)
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/* Other oses most likely use tpidr_el0 instead */
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uintptr_t c;
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asm volatile("mrs %x0, tpidrro_el0" : "=r"(c) :: "memory");
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return (malloc_cpuid_t)(c & (1 << 3) - 1);
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#else
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not_reached();
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return -1;
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#endif
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}
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/* Return the chosen arena index based on current cpu. */
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JEMALLOC_ALWAYS_INLINE unsigned
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percpu_arena_choose(void) {
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assert(have_percpu_arena && PERCPU_ARENA_ENABLED(opt_percpu_arena));
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malloc_cpuid_t cpuid = malloc_getcpu();
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assert(cpuid >= 0);
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unsigned arena_ind;
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if ((opt_percpu_arena == percpu_arena) || ((unsigned)cpuid < ncpus /
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2)) {
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arena_ind = cpuid;
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} else {
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assert(opt_percpu_arena == per_phycpu_arena);
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/* Hyper threads on the same physical CPU share arena. */
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arena_ind = cpuid - ncpus / 2;
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}
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return arena_ind;
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}
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/* Return the limit of percpu auto arena range, i.e. arenas[0...ind_limit). */
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JEMALLOC_ALWAYS_INLINE unsigned
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percpu_arena_ind_limit(percpu_arena_mode_t mode) {
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assert(have_percpu_arena && PERCPU_ARENA_ENABLED(mode));
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if (mode == per_phycpu_arena && ncpus > 1) {
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if (ncpus % 2) {
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/* This likely means a misconfig. */
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return ncpus / 2 + 1;
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}
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return ncpus / 2;
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} else {
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return ncpus;
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}
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}
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static inline arena_t *
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arena_get(tsdn_t *tsdn, unsigned ind, bool init_if_missing) {
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arena_t *ret;
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assert(ind < MALLOCX_ARENA_LIMIT);
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ret = (arena_t *)atomic_load_p(&arenas[ind], ATOMIC_ACQUIRE);
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if (unlikely(ret == NULL)) {
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if (init_if_missing) {
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ret = arena_init(tsdn, ind, &arena_config_default);
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}
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}
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return ret;
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}
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JEMALLOC_ALWAYS_INLINE bool
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tcache_available(tsd_t *tsd) {
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/*
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* Thread specific auto tcache might be unavailable if: 1) during tcache
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* initialization, or 2) disabled through thread.tcache.enabled mallctl
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* or config options. This check covers all cases.
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*/
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if (likely(tsd_tcache_enabled_get(tsd))) {
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/* Associated arena == NULL implies tcache init in progress. */
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if (config_debug && tsd_tcache_slowp_get(tsd)->arena != NULL) {
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tcache_assert_initialized(tsd_tcachep_get(tsd));
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}
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return true;
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}
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return false;
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}
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JEMALLOC_ALWAYS_INLINE tcache_t *
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tcache_get(tsd_t *tsd) {
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if (!tcache_available(tsd)) {
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return NULL;
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}
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return tsd_tcachep_get(tsd);
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}
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JEMALLOC_ALWAYS_INLINE tcache_slow_t *
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tcache_slow_get(tsd_t *tsd) {
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if (!tcache_available(tsd)) {
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return NULL;
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}
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return tsd_tcache_slowp_get(tsd);
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}
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static inline void
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pre_reentrancy(tsd_t *tsd, arena_t *arena) {
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/* arena is the current context. Reentry from a0 is not allowed. */
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assert(arena != arena_get(tsd_tsdn(tsd), 0, false));
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tsd_pre_reentrancy_raw(tsd);
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}
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static inline void
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post_reentrancy(tsd_t *tsd) {
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tsd_post_reentrancy_raw(tsd);
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}
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#endif /* JEMALLOC_INTERNAL_INLINES_A_H */
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