3d29d11ac2
Before this commit jemalloc produced many warnings when compiled with -Wextra
with both Clang and GCC. This commit fixes the issues raised by these warnings
or suppresses them if they were spurious at least for the Clang and GCC
versions covered by CI.
This commit:
* adds `JEMALLOC_DIAGNOSTIC` macros: `JEMALLOC_DIAGNOSTIC_{PUSH,POP}` are
used to modify the stack of enabled diagnostics. The
`JEMALLOC_DIAGNOSTIC_IGNORE_...` macros are used to ignore a concrete
diagnostic.
* adds `JEMALLOC_FALLTHROUGH` macro to explicitly state that falling
through `case` labels in a `switch` statement is intended
* Removes all UNUSED annotations on function parameters. The warning
-Wunused-parameter is now disabled globally in
`jemalloc_internal_macros.h` for all translation units that include
that header. It is never re-enabled since that header cannot be
included by users.
* locally suppresses some -Wextra diagnostics:
* `-Wmissing-field-initializer` is buggy in older Clang and GCC versions,
where it does not understanding that, in C, `= {0}` is a common C idiom
to initialize a struct to zero
* `-Wtype-bounds` is suppressed in a particular situation where a generic
macro, used in multiple different places, compares an unsigned integer for
smaller than zero, which is always true.
* `-Walloc-larger-than-size=` diagnostics warn when an allocation function is
called with a size that is too large (out-of-range). These are suppressed in
the parts of the tests where `jemalloc` explicitly does this to test that the
allocation functions fail properly.
* adds a new CI build bot that runs the log unit test on CI.
Closes #1196 .
194 lines
6.2 KiB
C
194 lines
6.2 KiB
C
#ifndef JEMALLOC_INTERNAL_ATOMIC_GCC_SYNC_H
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#define JEMALLOC_INTERNAL_ATOMIC_GCC_SYNC_H
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#define ATOMIC_INIT(...) {__VA_ARGS__}
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typedef enum {
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atomic_memory_order_relaxed,
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atomic_memory_order_acquire,
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atomic_memory_order_release,
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atomic_memory_order_acq_rel,
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atomic_memory_order_seq_cst
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} atomic_memory_order_t;
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ATOMIC_INLINE void
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atomic_fence(atomic_memory_order_t mo) {
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/* Easy cases first: no barrier, and full barrier. */
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if (mo == atomic_memory_order_relaxed) {
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asm volatile("" ::: "memory");
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return;
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}
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if (mo == atomic_memory_order_seq_cst) {
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asm volatile("" ::: "memory");
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__sync_synchronize();
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asm volatile("" ::: "memory");
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return;
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}
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asm volatile("" ::: "memory");
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# if defined(__i386__) || defined(__x86_64__)
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/* This is implicit on x86. */
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# elif defined(__ppc__)
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asm volatile("lwsync");
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# elif defined(__sparc__) && defined(__arch64__)
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if (mo == atomic_memory_order_acquire) {
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asm volatile("membar #LoadLoad | #LoadStore");
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} else if (mo == atomic_memory_order_release) {
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asm volatile("membar #LoadStore | #StoreStore");
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} else {
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asm volatile("membar #LoadLoad | #LoadStore | #StoreStore");
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}
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# else
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__sync_synchronize();
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# endif
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asm volatile("" ::: "memory");
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}
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/*
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* A correct implementation of seq_cst loads and stores on weakly ordered
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* architectures could do either of the following:
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* 1. store() is weak-fence -> store -> strong fence, load() is load ->
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* strong-fence.
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* 2. store() is strong-fence -> store, load() is strong-fence -> load ->
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* weak-fence.
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* The tricky thing is, load() and store() above can be the load or store
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* portions of a gcc __sync builtin, so we have to follow GCC's lead, which
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* means going with strategy 2.
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* On strongly ordered architectures, the natural strategy is to stick a strong
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* fence after seq_cst stores, and have naked loads. So we want the strong
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* fences in different places on different architectures.
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* atomic_pre_sc_load_fence and atomic_post_sc_store_fence allow us to
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* accomplish this.
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*/
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ATOMIC_INLINE void
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atomic_pre_sc_load_fence() {
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# if defined(__i386__) || defined(__x86_64__) || \
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(defined(__sparc__) && defined(__arch64__))
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atomic_fence(atomic_memory_order_relaxed);
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# else
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atomic_fence(atomic_memory_order_seq_cst);
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# endif
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}
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ATOMIC_INLINE void
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atomic_post_sc_store_fence() {
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# if defined(__i386__) || defined(__x86_64__) || \
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(defined(__sparc__) && defined(__arch64__))
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atomic_fence(atomic_memory_order_seq_cst);
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# else
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atomic_fence(atomic_memory_order_relaxed);
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# endif
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}
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#define JEMALLOC_GENERATE_ATOMICS(type, short_type, \
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/* unused */ lg_size) \
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typedef struct { \
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type volatile repr; \
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} atomic_##short_type##_t; \
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\
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ATOMIC_INLINE type \
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atomic_load_##short_type(const atomic_##short_type##_t *a, \
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atomic_memory_order_t mo) { \
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if (mo == atomic_memory_order_seq_cst) { \
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atomic_pre_sc_load_fence(); \
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} \
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type result = a->repr; \
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if (mo != atomic_memory_order_relaxed) { \
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atomic_fence(atomic_memory_order_acquire); \
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} \
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return result; \
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} \
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\
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ATOMIC_INLINE void \
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atomic_store_##short_type(atomic_##short_type##_t *a, \
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type val, atomic_memory_order_t mo) { \
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if (mo != atomic_memory_order_relaxed) { \
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atomic_fence(atomic_memory_order_release); \
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} \
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a->repr = val; \
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if (mo == atomic_memory_order_seq_cst) { \
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atomic_post_sc_store_fence(); \
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} \
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} \
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\
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ATOMIC_INLINE type \
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atomic_exchange_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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/* \
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* Because of FreeBSD, we care about gcc 4.2, which doesn't have\
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* an atomic exchange builtin. We fake it with a CAS loop. \
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*/ \
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while (true) { \
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type old = a->repr; \
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if (__sync_bool_compare_and_swap(&a->repr, old, val)) { \
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return old; \
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} \
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} \
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} \
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\
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ATOMIC_INLINE bool \
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atomic_compare_exchange_weak_##short_type(atomic_##short_type##_t *a, \
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type *expected, type desired, \
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atomic_memory_order_t success_mo, \
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atomic_memory_order_t failure_mo) { \
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type prev = __sync_val_compare_and_swap(&a->repr, *expected, \
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desired); \
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if (prev == *expected) { \
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return true; \
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} else { \
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*expected = prev; \
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return false; \
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} \
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} \
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ATOMIC_INLINE bool \
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atomic_compare_exchange_strong_##short_type(atomic_##short_type##_t *a, \
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type *expected, type desired, \
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atomic_memory_order_t success_mo, \
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atomic_memory_order_t failure_mo) { \
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type prev = __sync_val_compare_and_swap(&a->repr, *expected, \
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desired); \
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if (prev == *expected) { \
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return true; \
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} else { \
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*expected = prev; \
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return false; \
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} \
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}
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#define JEMALLOC_GENERATE_INT_ATOMICS(type, short_type, \
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/* unused */ lg_size) \
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JEMALLOC_GENERATE_ATOMICS(type, short_type, /* unused */ lg_size) \
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\
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ATOMIC_INLINE type \
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atomic_fetch_add_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_add(&a->repr, val); \
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} \
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\
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ATOMIC_INLINE type \
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atomic_fetch_sub_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_sub(&a->repr, val); \
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} \
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\
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ATOMIC_INLINE type \
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atomic_fetch_and_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_and(&a->repr, val); \
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} \
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\
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ATOMIC_INLINE type \
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atomic_fetch_or_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_or(&a->repr, val); \
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} \
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\
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ATOMIC_INLINE type \
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atomic_fetch_xor_##short_type(atomic_##short_type##_t *a, type val, \
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atomic_memory_order_t mo) { \
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return __sync_fetch_and_xor(&a->repr, val); \
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}
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#endif /* JEMALLOC_INTERNAL_ATOMIC_GCC_SYNC_H */
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